In the manufacturing steps of semiconductor, a substrate position alignment device (aligner) which aligns the rotational angle positions of a plurality of semiconductor wafers with a reference rotational angle position is used to conform the crystal directions of the semiconductor wafers to each other. To this end, the semiconductor wafers are provided with notches which are marks indicating the crystal directions of the semiconductor wafers, respectively. An example of the substrate position alignment device is disclosed in Patent Literature 1. In the substrate position alignment device disclosed in Patent Literature 1, three support poles are provided to extend vertically upward from the peripheral edge of one turn table, along the circumferential direction of the turn table, and each of the support poles is provided with five support pins which are equally spaced apart from each other in a vertical direction. The three support pins disposed at the same height position, of the three support poles, support the peripheral edge portion of one semiconductor wafer. On the outer side of the three support poles, three scooping poles are provided in such a manner that these scooping poles are movable up and down and are movable to be close to and away from the rotational center axis of the turn table. Each of the scooping poles is provided with five scooping pins which are equally spaced apart from each other in the vertical direction. A vertical spacing between adjacent scooping pins is set to be smaller than that of adjacent support pins. On the outer side of the three support poles, a sensor pole provided with a sensor for detecting the notches of the five semiconductor wafers supported by the support pins is provided.
Initially, each of the semiconductor wafers is supported by the three support pins disposed at the same height position. During a substrate position alignment operation, the turn table is rotated once, the sensor detects the notches to thereby detect the rotational angle positions of the notches of all of the semiconductor wafers, namely, misalignment angles from a reference rotational angle position, and the rotational angle positions are stored in a memory. Based on the rotational angle position stored in the memory, the turn table is rotated to align the rotational angle position of the lowermost semiconductor wafer (semiconductor wafer located at a lowermost position, of the plurality of semiconductor wafers) with the reference rotational angle position. Then, the three scooping poles are moved in an inward direction toward the turn table and moved up so that the scooping pins lift-up the lowermost semiconductor wafer for which the alignment of the rotational angle position is completed. As described above, the vertical spacing between adjacent scooping pins is set to be smaller than that of the adjacent support pins. Therefore, while maintaining a state in which only the lowermost semiconductor wafer is scooped up, the remaining four semiconductor wafers continue to be placed on the support pins. Then, based on the rotational angle position stored in the memory, the turn table is rotated to align the rotational angle position of the second semiconductor wafer from the bottom with the reference rotational angle position, and this semiconductor wafer is scooped up by the scooping pins in the above-described manner. In this way, the rotational angle positions of the five semiconductor wafers are sequentially aligned with the reference rotational angle position.